CPU event definitions for LA/LE. More...

Macros
#define	ITRACE_CPU_EVENT_SYSFS_CORE_0_CLK_FREQ_HZ 0x0
	Clock frequency (in Hz) of core 0.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_1_CLK_FREQ_HZ 0x1
	Clock frequency (in Hz) of core 1.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_2_CLK_FREQ_HZ 0x2
	Clock frequency (in Hz) of core 2.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_3_CLK_FREQ_HZ 0x3
	Clock frequency (in Hz) of core 3.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_4_CLK_FREQ_HZ 0x4
	Clock frequency (in Hz) of core 4.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_5_CLK_FREQ_HZ 0x5
	Clock frequency (in Hz) of core 5.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_6_CLK_FREQ_HZ 0x6
	Clock frequency (in Hz) of core 6.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_7_CLK_FREQ_HZ 0x7
	Clock frequency (in Hz) of core 7.

#define	ITRACE_CPU_EVENT_SYSFS_CLK_FREQ_HZ 0x8
	Clock frequency (in Hz) of current core.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_0_CLK_FREQ_HZ 0x9
	Clock frequency (in Hz) of core 0.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_1_CLK_FREQ_HZ 0xa
	Clock frequency (in Hz) of core 1.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_2_CLK_FREQ_HZ 0xb
	Clock frequency (in Hz) of core 2.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_3_CLK_FREQ_HZ 0xc
	Clock frequency (in Hz) of core 3.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_4_CLK_FREQ_HZ 0xd
	Clock frequency (in Hz) of core 4.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_5_CLK_FREQ_HZ 0xe
	Clock frequency (in Hz) of core 5.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_6_CLK_FREQ_HZ 0xf
	Clock frequency (in Hz) of core 6.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_7_CLK_FREQ_HZ 0x10
	Clock frequency (in Hz) of core 7.

#define	ITRACE_CPU_EVENT_FTRACE_CLK_FREQ_HZ 0x11
	Clock frequency (in Hz) of current core.

#define	ITRACE_CPU_EVENT_PERF_SW_TASK_CLOCK 0x12
	Clock count specific to the current task.

#define	ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS 0x13
	Page fault count.

#define	ITRACE_CPU_EVENT_PERF_SW_CONTEXT_SWITCHES 0x14
	Context switches count.

#define	ITRACE_CPU_EVENT_PERF_SW_CPU_MIGRATIONS 0x15
	Count for the number of times the process has migrated to a new CPU.

#define	ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS_MIN 0x16
	Minor page fault count.

#define	ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS_MAJ 0x17
	Major page fault count.

#define	ITRACE_CPU_EVENT_PERF_SW_ALIGNMENT_FAULTS 0x18
	Alignment fault count.

#define	ITRACE_CPU_EVENT_PERF_SW_EMULATION_FAULTS 0x19
	Emulation fault count.

#define	ITRACE_CPU_EVENT_PERF_HW_CPU_CYCLES 0x1a
	Cycle count.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_REFERENCES 0x1b
	Cache references.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_MISSES 0x1c
	Cache misses.

#define	ITRACE_CPU_EVENT_PERF_HW_BRANCH_MISSES 0x1d
	Branch misses.

#define	ITRACE_CPU_EVENT_PERF_HW_BUS_CYCLES 0x1e
	Bus cycle count.

#define	ITRACE_CPU_EVENT_PERF_HW_STALLED_CYCLES_FRONTEND 0x1f
	Stalled cycles during issue.

#define	ITRACE_CPU_EVENT_PERF_HW_STALLED_CYCLES_BACKEND 0x20
	Stalled cycles during retirement.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1D_READ_ACCESS 0x21
	Level 1 Data Cache Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1D_READ_MISS 0x22
	Level 1 Data Cache Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1I_READ_ACCESS 0x23
	Level 1 Instruction Cache Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1I_READ_MISS 0x24
	Level 1 Instruction Cache Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_LL_READ_ACCESS 0x25
	Last-Level Cache Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_LL_READ_MISS 0x26
	Last-Level Cache Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_DTLB_READ_ACCESS 0x27
	Data TLB Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_DTLB_READ_MISS 0x28
	Data TLB Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_ITLB_READ_ACCESS 0x29
	Instruction TLB Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_ITLB_READ_MISS 0x2a
	Instruction TLB Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_BPU_READ_ACCESS 0x2b
	Branch Prediction Unit Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_BPU_READ_MISS 0x2c
	Branch Prediction Unit Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_NODE_READ_ACCESS 0x2d
	Local Memory Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_NODE_READ_MISS 0x2e
	Local Memory Read Misses.

#define	ITRACE_CPU_EVENT_MEMINFO_MEMTOTAL 0x2f
	Total amount of usable memory.

#define	ITRACE_CPU_EVENT_MEMINFO_MEMFREE 0x30
	The amount of physical memory not used by the system.

#define	ITRACE_CPU_EVENT_MEMINFO_MEMAVAILABLE 0x31
	An estimate of how much memory is available for starting new applications.

#define	ITRACE_CPU_EVENT_MEMINFO_BUFFERS 0x32
	Amount of memory in buffer cache. The amount of temporary storage for raw disk blocks.

#define	ITRACE_CPU_EVENT_MEMINFO_CACHED 0x33
	Amount of memory used as cache memory.

#define	ITRACE_CPU_EVENT_MEMINFO_SWAPCACHED 0x34
	Amount of memory that is present within the main memory and also the swapfile.

#define	ITRACE_CPU_EVENT_MEMINFO_ACTIVE 0x35
	Amount of memory that has been used more recently and is usually not reclaimed or swapped out.

#define	ITRACE_CPU_EVENT_MEMINFO_INACTIVE 0x36
	Amount of memory that has not been used recently and is more eligible to be reclaimed or swapped out.

#define	ITRACE_CPU_EVENT_MEMINFO_UNEVICTABLE 0x37
	Amount of memory that is locked into memory by user programs and thus is not evictable.

#define	ITRACE_CPU_EVENT_MEMINFO_MLOCKED 0x38
	Amount of memory that is page locked to memory using the mlock() system calls. Mlocked pages are also Unevictable.

#define	ITRACE_CPU_EVENT_MEMINFO_SWAPTOTAL 0x39
	Total amount of swap space available.

#define	ITRACE_CPU_EVENT_MEMINFO_SWAPFREE 0x3a
	Total amount of swap free available.

#define	ITRACE_CPU_EVENT_MEMINFO_DIRTY 0x3b
	Amount of memory waiting to be written back to the disk.

#define	ITRACE_CPU_EVENT_MEMINFO_WRITEBACK 0x3c
	Amount of memory actively being written back to the disk.

#define	ITRACE_CPU_EVENT_MEMINFO_ANONPAGES 0x3d
	Amount of memory used by pages that are not mapped into userspace page tables.

#define	ITRACE_CPU_EVENT_MEMINFO_MAPPED 0x3e
	Amount of memory used for files that have been mmaped (such as libraries)

#define	ITRACE_CPU_EVENT_MEMINFO_SHMEM 0x3f
	Amount of shared memory used.

#define	ITRACE_CPU_EVENT_MEMINFO_KRECLAIMABLE 0x40
	Amount of kernel allocations (including slab) that can be reclaimed.

#define	ITRACE_CPU_EVENT_MEMINFO_SLAB 0x41
	Amount of memory used by in-kernel data structures.

#define	ITRACE_CPU_EVENT_MEMINFO_SRECLAIMABLE 0x42
	Amount of slab that can be reclaimed (such as caches)

#define	ITRACE_CPU_EVENT_MEMINFO_SUNRECLAIM 0x43
	Amount of slab that cannot be reclaimed.

#define	ITRACE_CPU_EVENT_MEMINFO_KERNELSTACK 0x44
	Amount of memory used by the kernel stack. This cannot be reclaimed.

#define	ITRACE_CPU_EVENT_MEMINFO_SHADOWCALLSTACK 0x45
	Amount of memory usage associated with the ShadowCallStack feature.

#define	ITRACE_CPU_EVENT_MEMINFO_PAGETABLES 0x46
	Amount of memory dedicated to the lowest page table level.

#define	ITRACE_CPU_EVENT_MEMINFO_SECPAGETABLES 0x47
	Amount of memory dedicated to secure page tables.

#define	ITRACE_CPU_EVENT_MEMINFO_NFS_UNSTABLE 0x48
	Amount of NFS pages sent to the server but not yet committed to storage.

#define	ITRACE_CPU_EVENT_MEMINFO_BOUNCE 0x49
	Amount of memory used for block device "bounce buffers".

#define	ITRACE_CPU_EVENT_MEMINFO_WRITEBACKTMP 0x4a
	Amount of memory used by FUSE for temporary writeback buffers.

#define	ITRACE_CPU_EVENT_MEMINFO_COMMITLIMIT 0x4b
	Amount of memory currently available to be allocated on the system.

#define	ITRACE_CPU_EVENT_MEMINFO_COMMITTED_AS 0x4c
	Amount of memory currently allocated on the system.

#define	ITRACE_CPU_EVENT_MEMINFO_VMALLOCTOTAL 0x4d
	Amount of memory of total allocated virtual address space.

#define	ITRACE_CPU_EVENT_MEMINFO_VMALLOCUSED 0x4e
	Amount of memory of used virtual address space.

#define	ITRACE_CPU_EVENT_MEMINFO_VMALLOCCHUNK 0x4f
	Largest contiguous block of memory of available virtual address space.

#define	ITRACE_CPU_EVENT_MEMINFO_PERCPU 0x50
	Amount of memory dedicated to per-cpu objects.

#define	ITRACE_CPU_EVENT_MEMINFO_ANONHUGEPAGES 0x51
	Amount of memory used by non-file backed huge pages that are mapped into userspace tables.

#define	ITRACE_CPU_EVENT_MEMINFO_CMATOTAL 0x52
	Amount of contiguous memory area reserved for the current kernel.

#define	ITRACE_CPU_EVENT_MEMINFO_CMAFREE 0x53
	Amount of contiguous memory area that is free to use by the current kernel.

#define	ITRACE_NUMBER_DEFINED_CPU_EVENTS 0x54
	Number of supported CPU events.

#define	MAX_NUMBER_CPU_PMUS 3
	Maximum number of hardware events that can monitored.

Detailed Description

CPU event definitions for LA/LE.

=============================================================================

itrace_cpu_events_la.h

Note: This file is automatically generated.

Macros

Detailed Description

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