CPU perf hardware cache event definitions

Macros
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1D_READ_ACCESS   0x21
	Level 1 Data Cache Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1D_READ_MISS   0x22
	Level 1 Data Cache Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1I_READ_ACCESS   0x23
	Level 1 Instruction Cache Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1I_READ_MISS   0x24
	Level 1 Instruction Cache Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_LL_READ_ACCESS   0x25
	Last-Level Cache Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_LL_READ_MISS   0x26
	Last-Level Cache Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_DTLB_READ_ACCESS   0x27
	Data TLB Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_DTLB_READ_MISS   0x28
	Data TLB Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_ITLB_READ_ACCESS   0x29
	Instruction TLB Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_ITLB_READ_MISS   0x2a
	Instruction TLB Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_BPU_READ_ACCESS   0x2b
	Branch Prediction Unit Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_BPU_READ_MISS   0x2c
	Branch Prediction Unit Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_NODE_READ_ACCESS   0x2d
	Local Memory Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_NODE_READ_MISS   0x2e
	Local Memory Read Misses.

Detailed Description