CPU event definitions for LA/LE. More...

Macros
#define	DUMMY_CPU_EVENT_FIRST 0x6fff
	Dummy first event to help calculate ITRACE_NUMBER_DEFINED_CPU_EVENTS.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_0_CLK_FREQ_HZ 0x7000
	Clock frequency (in Hz) of core 0.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_1_CLK_FREQ_HZ 0x7001
	Clock frequency (in Hz) of core 1.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_2_CLK_FREQ_HZ 0x7002
	Clock frequency (in Hz) of core 2.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_3_CLK_FREQ_HZ 0x7003
	Clock frequency (in Hz) of core 3.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_4_CLK_FREQ_HZ 0x7004
	Clock frequency (in Hz) of core 4.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_5_CLK_FREQ_HZ 0x7005
	Clock frequency (in Hz) of core 5.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_6_CLK_FREQ_HZ 0x7006
	Clock frequency (in Hz) of core 6.

#define	ITRACE_CPU_EVENT_SYSFS_CORE_7_CLK_FREQ_HZ 0x7007
	Clock frequency (in Hz) of core 7.

#define	ITRACE_CPU_EVENT_SYSFS_CLK_FREQ_HZ 0x7008
	Clock frequency (in Hz) of current core.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_0_CLK_FREQ_HZ 0x7009
	Clock frequency (in Hz) of core 0.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_1_CLK_FREQ_HZ 0x700a
	Clock frequency (in Hz) of core 1.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_2_CLK_FREQ_HZ 0x700b
	Clock frequency (in Hz) of core 2.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_3_CLK_FREQ_HZ 0x700c
	Clock frequency (in Hz) of core 3.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_4_CLK_FREQ_HZ 0x700d
	Clock frequency (in Hz) of core 4.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_5_CLK_FREQ_HZ 0x700e
	Clock frequency (in Hz) of core 5.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_6_CLK_FREQ_HZ 0x700f
	Clock frequency (in Hz) of core 6.

#define	ITRACE_CPU_EVENT_FTRACE_CORE_7_CLK_FREQ_HZ 0x7010
	Clock frequency (in Hz) of core 7.

#define	ITRACE_CPU_EVENT_FTRACE_CLK_FREQ_HZ 0x7011
	Clock frequency (in Hz) of current core.

#define	ITRACE_CPU_EVENT_PERF_SW_TASK_CLOCK 0x7012
	Clock count specific to the current task.

#define	ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS 0x7013
	Page fault count.

#define	ITRACE_CPU_EVENT_PERF_SW_CONTEXT_SWITCHES 0x7014
	Context switches count.

#define	ITRACE_CPU_EVENT_PERF_SW_CPU_MIGRATIONS 0x7015
	Count for the number of times the process has migrated to a new CPU.

#define	ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS_MIN 0x7016
	Minor page fault count.

#define	ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS_MAJ 0x7017
	Major page fault count.

#define	ITRACE_CPU_EVENT_PERF_SW_ALIGNMENT_FAULTS 0x7018
	Alignment fault count.

#define	ITRACE_CPU_EVENT_PERF_SW_EMULATION_FAULTS 0x7019
	Emulation fault count.

#define	ITRACE_CPU_EVENT_PERF_HW_CPU_CYCLES 0x701a
	Cycle count.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_REFERENCES 0x701b
	Cache references.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_MISSES 0x701c
	Cache misses.

#define	ITRACE_CPU_EVENT_PERF_HW_BRANCH_MISSES 0x701d
	Branch misses.

#define	ITRACE_CPU_EVENT_PERF_HW_BUS_CYCLES 0x701e
	Bus cycle count.

#define	ITRACE_CPU_EVENT_PERF_HW_STALLED_CYCLES_FRONTEND 0x701f
	Stalled cycles during issue.

#define	ITRACE_CPU_EVENT_PERF_HW_STALLED_CYCLES_BACKEND 0x7020
	Stalled cycles during retirement.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1D_READ_ACCESS 0x7021
	Level 1 Data Cache Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1D_READ_MISS 0x7022
	Level 1 Data Cache Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1I_READ_ACCESS 0x7023
	Level 1 Instruction Cache Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1I_READ_MISS 0x7024
	Level 1 Instruction Cache Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_LL_READ_ACCESS 0x7025
	Last-Level Cache Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_LL_READ_MISS 0x7026
	Last-Level Cache Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_DTLB_READ_ACCESS 0x7027
	Data TLB Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_DTLB_READ_MISS 0x7028
	Data TLB Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_ITLB_READ_ACCESS 0x7029
	Instruction TLB Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_ITLB_READ_MISS 0x702a
	Instruction TLB Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_BPU_READ_ACCESS 0x702b
	Branch Prediction Unit Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_BPU_READ_MISS 0x702c
	Branch Prediction Unit Read Misses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_NODE_READ_ACCESS 0x702d
	Local Memory Read Accesses.

#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_NODE_READ_MISS 0x702e
	Local Memory Read Misses.

#define	ITRACE_CPU_EVENT_MEMINFO_MEMTOTAL 0x702f
	Total amount of usable memory.

#define	ITRACE_CPU_EVENT_MEMINFO_MEMFREE 0x7030
	The amount of physical memory not used by the system.

#define	ITRACE_CPU_EVENT_MEMINFO_MEMAVAILABLE 0x7031
	An estimate of how much memory is available for starting new applications.

#define	ITRACE_CPU_EVENT_MEMINFO_BUFFERS 0x7032
	Amount of memory in buffer cache. The amount of temporary storage for raw disk blocks.

#define	ITRACE_CPU_EVENT_MEMINFO_CACHED 0x7033
	Amount of memory used as cache memory.

#define	ITRACE_CPU_EVENT_MEMINFO_SWAPCACHED 0x7034
	Amount of memory that is present within the main memory and also the swapfile.

#define	ITRACE_CPU_EVENT_MEMINFO_ACTIVE 0x7035
	Amount of memory that has been used more recently and is usually not reclaimed or swapped out.

#define	ITRACE_CPU_EVENT_MEMINFO_INACTIVE 0x7036
	Amount of memory that has not been used recently and is more eligible to be reclaimed or swapped out.

#define	ITRACE_CPU_EVENT_MEMINFO_UNEVICTABLE 0x7037
	Amount of memory that is locked into memory by user programs and thus is not evictable.

#define	ITRACE_CPU_EVENT_MEMINFO_MLOCKED 0x7038
	Amount of memory that is page locked to memory using the mlock() system calls. Mlocked pages are also Unevictable.

#define	ITRACE_CPU_EVENT_MEMINFO_SWAPTOTAL 0x7039
	Total amount of swap space available.

#define	ITRACE_CPU_EVENT_MEMINFO_SWAPFREE 0x703a
	Total amount of swap free available.

#define	ITRACE_CPU_EVENT_MEMINFO_DIRTY 0x703b
	Amount of memory waiting to be written back to the disk.

#define	ITRACE_CPU_EVENT_MEMINFO_WRITEBACK 0x703c
	Amount of memory actively being written back to the disk.

#define	ITRACE_CPU_EVENT_MEMINFO_ANONPAGES 0x703d
	Amount of memory used by pages that are not mapped into userspace page tables.

#define	ITRACE_CPU_EVENT_MEMINFO_MAPPED 0x703e
	Amount of memory used for files that have been mmaped (such as libraries)

#define	ITRACE_CPU_EVENT_MEMINFO_SHMEM 0x703f
	Amount of shared memory used.

#define	ITRACE_CPU_EVENT_MEMINFO_KRECLAIMABLE 0x7040
	Amount of kernel allocations (including slab) that can be reclaimed.

#define	ITRACE_CPU_EVENT_MEMINFO_SLAB 0x7041
	Amount of memory used by in-kernel data structures.

#define	ITRACE_CPU_EVENT_MEMINFO_SRECLAIMABLE 0x7042
	Amount of slab that can be reclaimed (such as caches)

#define	ITRACE_CPU_EVENT_MEMINFO_SUNRECLAIM 0x7043
	Amount of slab that cannot be reclaimed.

#define	ITRACE_CPU_EVENT_MEMINFO_KERNELSTACK 0x7044
	Amount of memory used by the kernel stack. This cannot be reclaimed.

#define	ITRACE_CPU_EVENT_MEMINFO_SHADOWCALLSTACK 0x7045
	Amount of memory usage associated with the ShadowCallStack feature.

#define	ITRACE_CPU_EVENT_MEMINFO_PAGETABLES 0x7046
	Amount of memory dedicated to the lowest page table level.

#define	ITRACE_CPU_EVENT_MEMINFO_SECPAGETABLES 0x7047
	Amount of memory dedicated to secure page tables.

#define	ITRACE_CPU_EVENT_MEMINFO_NFS_UNSTABLE 0x7048
	Amount of NFS pages sent to the server but not yet committed to storage.

#define	ITRACE_CPU_EVENT_MEMINFO_BOUNCE 0x7049
	Amount of memory used for block device "bounce buffers".

#define	ITRACE_CPU_EVENT_MEMINFO_WRITEBACKTMP 0x704a
	Amount of memory used by FUSE for temporary writeback buffers.

#define	ITRACE_CPU_EVENT_MEMINFO_COMMITLIMIT 0x704b
	Amount of memory currently available to be allocated on the system.

#define	ITRACE_CPU_EVENT_MEMINFO_COMMITTED_AS 0x704c
	Amount of memory currently allocated on the system.

#define	ITRACE_CPU_EVENT_MEMINFO_VMALLOCTOTAL 0x704d
	Amount of memory of total allocated virtual address space.

#define	ITRACE_CPU_EVENT_MEMINFO_VMALLOCUSED 0x704e
	Amount of memory of used virtual address space.

#define	ITRACE_CPU_EVENT_MEMINFO_VMALLOCCHUNK 0x704f
	Largest contiguous block of memory of available virtual address space.

#define	ITRACE_CPU_EVENT_MEMINFO_PERCPU 0x7050
	Amount of memory dedicated to per-cpu objects.

#define	ITRACE_CPU_EVENT_MEMINFO_ANONHUGEPAGES 0x7051
	Amount of memory used by non-file backed huge pages that are mapped into userspace tables.

#define	ITRACE_CPU_EVENT_MEMINFO_CMATOTAL 0x7052
	Amount of contiguous memory area reserved for the current kernel.

#define	ITRACE_CPU_EVENT_MEMINFO_CMAFREE 0x7053
	Amount of contiguous memory area that is free to use by the current kernel.

#define	DUMMY_CPU_EVENT_LAST 0x7054
	Dummy last event to help calculate ITRACE_NUMBER_DEFINED_CPU_EVENTS.

#define	ITRACE_CPU_EVENT_OFFSET (DUMMY_CPU_EVENT_FIRST+1)
	Offset to the first CPU event id.

#define	ITRACE_NUMBER_DEFINED_CPU_EVENTS (DUMMY_CPU_EVENT_LAST-DUMMY_CPU_EVENT_FIRST-1)
	Number of supported CPU events.

#define	ITRACE_MAX_NUMBER_REGISTERED_CPU_PMU_EVENTS 3
	Maximum number of hardware events that can monitored.

Detailed Description

CPU event definitions for LA/LE.

=============================================================================

Note: This file is automatically generated.

Macros

Detailed Description

All Rights Reserved. Qualcomm Proprietary and Confidential.